The present invention relates to a DC-DC converter, and more particularly, to a circuit and method for controlling a DC-DC converter.
In recent years, an electronic device, such as a portable device or a peripheral device (e.g., a hard disk drive (HDD)) connected to a personal computer or a notebook personal computer generally includes a rechargeable secondary battery, which is used as a drive power supply, and a circuit for charging the secondary battery. The electronic device is connected to an external power supply of an AC adaptor or a personal computer to charge the secondary battery with current supplied from the external power supply when the electronic device is not operating. Further, when the consumption current of the electronic device is lower than the current supplied from the external power supply (rated current) during operation, the electronic device charges the secondary battery by supplying the secondary battery with charging current, which is less than the rated current. However, the consumption current of the electronic device may temporarily exceed the rated current of the external power supply depending on the operation state of the electronic device. When the consumption current of the electronic device exceeds the rated current of the external power supply, the operation of the electronic device may become unstable. Thus, the electronic device is required to operate in a stable manner even when its consumption current exceeds the rated current of the external power supply.
Japanese Laid-Open Patent Publication No. 8-182219 describes an electronic device including a charging circuit. The charging circuit charges a secondary battery with power supplied from an external power supply.
FIG. 1 is a schematic circuit diagram of a prior art charging circuit 10.
The charging circuit 10 is formed by a DC-DC converter. The charging circuit 10 lowers an input voltage Vin, which is supplied via, for example, a universal serial bus (USB) interface of a personal computer to generate first output voltage Vout1. The first output voltage Vout1 is supplied to a secondary battery BAT. The charging circuit 10 also generates second output voltage Vout2 from the input voltage Vin. The second output voltage Vout2 is supplied to a load (not shown), such as an internal circuit. A current measuring resistor RS1 is arranged in the path for supplying the second output voltage Vout2. The charging circuit 10 controls the amount of current supplied to the secondary battery based on the current flowing through the resistor RS1.
The charging circuit 10 includes a control circuit 11, transistors FET1 and FET2, a choke coil L1, a smoothing capacitor C1, current measuring resistors RS1 and RS2 (hereafter referred to as the first resistor RS1 and the second resistor RS2), and a diode D1. The control circuit 11 includes a first voltage amplifier AMP1 having two input terminals, which are respectively connected to the two terminals of the first resistor RS1 and which receives signals CS1 and FB1 indicating the potentials at the two terminals of the first resistor RS1. The first voltage amplifier AMP1 detects a potential difference between the two terminals of the first resistor RS1, that is, the potential that is in accordance with the current flowing through the first resistor RS1. The control circuit 11 further includes a second voltage amplifier AMP2 having two input terminals, which are respectively connected to the two terminals of the second resistor RS2 and which receives signals CS2 and FB2 indicating the potentials at the two terminals of the second resistor RS2. The second voltage amplifier AMP2 detects the potential difference between the two terminals of the second resistor RS2, that is, the potential that is in accordance with the current flowing through the second resistor RS2. The resistors R1 and R2 generate a divided voltage by dividing the voltage of the signal FB2, or the output voltage Vout1.
A first error amplifier ERA1 generates a first error signal Vop1 by amplifying the difference between the output voltage of the first voltage amplifier AMP1 and the voltage of a reference power supply e1. A second error amplifier ERA2 generates a second error signal Vop2 by amplifying the difference between the output voltage of the second voltage amplifier AMP2 and the voltage of a reference power supply e2. A third error amplifier ERA3 generates a third error signal Vop3 by amplifying the difference between the divided voltage and the voltage of a reference power supply e3.
A pulse-width modulation (PWM) comparator 100 compares a triangular wave signal generated by an oscillator OSC with the first to third error signals Vop1, Vop2, and Vop3 to generate complementary first and second control signals DH and DL, each having a pulse width that is in accordance with the comparison result. In detail, the PWM comparator 100 are has non-inversion input terminals supplied with the first to third error signals Vop1, Vop2, and Vop3 and an inversion input terminal provided with the triangular wave signal. The PWM comparator 100 compares the one of the first to third error signals Vop1, Vop2, and Vop3 having the lowest voltage with the triangular wave signal. The PWM comparator 100 then generates a high (H) level first control signal DH when the voltage of the triangular wave signal is higher than the voltage of the error signal and generates a low (L) level first control signal DH when the voltage of the error signal is lower than the voltage of the triangular wave signal. The PWM comparator 100 further generates a second control signal DL having an inverted level of the first control signal DH. The first control signal DH is provided to the gate of the first transistor FET1. The second control signal DL is provided to the gate of the second transistor FET2.
The first transistor FET1 and the second transistor FET2 are N-channel metal oxide semiconductor (MOS) transistors. The first transistor FET1 and the second transistor FET2 are each activated in response to an H level gate signal and inactivated in response to an L level gate signal. The first transistor FET1 and the second transistor FET2 are activated and inactivated in a complementary manner in response to the first control signal DH and the second control signal DL. The activated period (or the inactivated period) of each of the transistors FET1 and FET2 is controlled based on the voltage of each of the first to third error signals Vop1, Vop2, and Vop3.
The operation of the charging circuit 10 will now be described.
When the first transistor FET1 is activated, the secondary battery BAT is supplied with current from the input voltage Vin via the choke coil L1. The current flowing through the choke coil L1 increases as time elapses in accordance with the voltage difference between the input voltage Vin and the output voltage Vout1. As a result, the current supplied to the secondary battery also increases. Further, as current flows through the choke coil L1, energy is accumulated in the choke coil L1.
When the first transistor FET1 is inactivated, the second transistor FET2, which is for synchronous rectification, is activated. This discharges the energy accumulated in the choke coil L1.
The output voltage Vout1 is expressed below.Vout1=(Ton/(Ton+Toff))*Vin=(Ton/T)*Vin 
In the expression, Ton is the period during which the first transistor FET is activated and Toff is the period during which the first transistor FET1 is inactivated. Here, T=Ton+Toff is satisfied.
The current flowing through the choke coil L1 flows toward the secondary battery BAT via the transistor FET1 during the period the first transistor FET1 is on. Thus, the average value of a current Iin flowing through the first transistor FET1 is equal to the product of the output current Iout and the duty of the transistor FET1 and expressed by the equation shown below.Iin=(Ton/T)*Iout
Based on the above expression, the control circuit 11 compensates for a change in the input voltage Vin by controlling the duty of the transistor FET1. The control circuit 11 further compensates for a change in the output voltage Vout1 that may occur when the consumption current of the load fluctuations by detecting the output voltage Vout1 and controlling the duty of the transistor FET1. This keeps the output voltage Vout constant.
When the consumption current of the load increases, the current flowing through the first resistor RS1 increases. As a result, the voltage drop caused by the first resistor RS1 increases. This decreases the difference between the output voltage of the first voltage amplifier AMP1 and the voltage of the reference power supply e1 and lowers the voltage of the first error signal Vop1. As a result, the output pulse width of the PWM comparator 100 is narrowed, and the activated period of the transistor FET1 is shortened. In this case, the output voltage Vout1 decreases, and the charging current of the secondary battery BAT decreases.
When the consumption current of the load decreases, the current flowing through the first resistor RS1 decreases. As a result, the voltage drop caused by the first resistor RS1 decreases. This increases the difference between the output voltage of the first voltage amplifier AMP1 and the voltage of the reference power supply e1 and increases the voltage of the first error signal Vop1. As a result, the output pulse width of the PWM comparator 100 is widened, and the activated period of the transistor FET1 is lengthened. In this case, the output voltage Vout1 increases, and the charging current of the secondary battery BAT increases.
In this manner, the charging circuit 10 controls the charging current of the secondary battery BAT in accordance with the amount of consumption current of the load by controlling the duty of the transistor FET1 (the ratio of the activated period and the inactivated period). As a result, the input current of the charging circuit 10 is controlled in a manner that it does not exceed the rated current of the external power supply.
However, the consumption current of the load may increase transiently. For example, an HDD starts driving its spindle motor when activated. Thus, the HDD requires a greater power when the HDD is activated than when the spindle motor is being driven at constant rotation velocity. However, the current supplying capability of the USB interface is limited. Accordingly, it is difficult to drive an electronic device that temporarily requires a large amount of current, such as an HDD, with only the power supplied through the USB.
Japanese Laid-Open Patent Publication No. 2000-029544 describes a circuit for monitoring the consumption current of a load. When the consumption current of the load exceeds the rated current of an external power supply, a secondary battery BAT is used to compensate for the insufficient amount of current. However, the charging circuit 10 shown in FIG. 1 supplies current from the secondary battery BAT to the load via the diode D1. Further, the voltage of the secondary battery BAT is lower than the input voltage Vin. Thus, it is impossible to supply current from the secondary battery BAT to the load when the input voltage Vin is being supplied. In other words, the charging circuit 10 fails to perform an appropriate charging operation when a transient load fluctuation occurs. To solve this problem, for example, a charging circuit 20 (DC-DC converter) shown in FIG. 2 may be used.
The charging circuit 20 supplies output voltage Vout2 to a load connected to a node between a choke coil L1 and a current measuring resistor RS2. A secondary battery BAT is connected to the load via the current measuring resistor RS2. Thus, current is supplied from the secondary battery BAT to the load even when the input voltage Vin is being supplied. In other words, the charging circuit 20 performs an appropriate charging operation when a transient load fluctuation occurs.